The present invention relates to solid-state imaging apparatus for use for example in digital cameras, and more particularly relates to solid-state imaging apparatus having a concurrent shutter function where it is made possible to reduce the number of wirings within a pixel section.
The construction as shown in FIG. 1 has been disclosed for example in Japanese Patent Application Laid-Open hei-11-261896 as a pixel of the pixel section to be used in the solid-state imaging apparatus having a concurrent shutter (referred to also as a global shutter) function. FIG. 1 includes: a photoelectric conversion means 1 such as photodiode for receiving light for a predetermined time to effect its photoelectric conversion by accumulating photoelectric charges; a memory means 2 for retaining photoelectric charges of the photoelectric conversion means 1; a transfer means 3 for transferring photoelectric charges of the photoelectric conversion means 1 to the memory means 2; a reset means 4 for resetting the memory means 2 to a power supply potential; a discharge means 5 for resetting the photoelectric conversion means 1 to a power supply potential; and a read means 6 for reading the electric charges of the memory means 2. A plurality of unit pixels 7 each constituted of these means are two-dimensionally arranged to form a pixel section. What is denoted by numeral 8 is a vertical signal line for outputting a signal read out by the read means 6.
Also referring to FIG. 1, φ TX1(n), φ RES(n), φ TX2(n), and φ SEL(n) are a transfer control signal, reset control signal, discharge control signal, and read control signal, respectively, for controlling ON and OFF of the transfer means 3, the reset means 4, the discharge means 5, and the read means 6. It should be noted that the suffix (n) of φ TX1(n), φ RES(n), φ TX2(n), and φ SEL(n) represents the location of row, and these control signals are respectively outputted to each row of the pixel section from a vertical circuit to be described in the following.
FIG. 2 shows an example of construction of the prior-art solid-state imaging apparatus having a concurrent shutter function where pixels of the construction shown in FIG. 1 are used. In the pixel section of the illustrated example, only a portion consisting of a 4×4 array of 16 pixels is shown. FIG. 2 includes: a vertical circuit 9; a horizontal circuit 10 for selecting a vertical signal line 8 so as to output the signal of pixel associated with a pixel column which is connected to that vertical signal line; and a controller 13 for controlling operation of the vertical circuit 9 and the horizontal circuit 10.
An operation of the pixel section of the solid-state imaging apparatus shown in FIG. 2 will be described below with reference to a timing chart shown in FIG. 3. In the timing chart shown in FIG. 3, operation timing is shown with assuming a pixel section having seven pixel rows. As shown in FIG. 3, by concurrently driving the discharge control signal φ TX2(n) of all pixels to H level, a concurrent discharge operation of all pixels is started by the discharge means 5. At a point in time t1 after passage of a predetermined time, the discharge control signal φ TX2(n) is brought to L level concurrently of all pixels. A concurrent discharge/reset operation of all pixels is thus completed by the discharge means 5 so that an exposure of all pixels is started.
After passage of a predetermined exposure time, the transfer means 3 is turned ON concurrently of all pixels by the transfer control signal φ TX1(n) at a timing of concurrent transfer of all pixels so that photoelectric charges accumulated at the photoelectric conversion means 1 are concurrently transferred to the memory means 2 (time t2). In other words, the exposure is ended. Here in the timing chart shown in FIG. 3, the period from time t1 to time t2 constitutes an actual exposure period. When the exposure is ended, a reading of signal levels is then started sequentially beginning from the first row with using the read means 6 by the read control signal φ SEL(n).